How to decrease the frequency of a CLK?

In digital circuits, we have heard of circuit called divided by circuit. However, when I asked a question in interview -"If we have 100Hz clock,how can we get 50Hz clock?"- the candidate failed to answer. Even the candidate did not understand the clock means. Generally, many people have confusion between a clock signal and a square wave. Clock signal is a square pulses. The clock and square wave is shown in below image.

The square wave has negative excursion but that is not the case with square pulses(=clock).

The digital circuit elements- flip flops- help us to implement divided by circuits. The circuit for above said question is shown below.

The frequency is divide by 2 in this case. However, the period (in time ) it is doubled. Any odd number of divided by circuit can be implemented by having appropriate mod-x counters(where x is a integer).The wave form is shown below:

By using DFF, we can divide the clock frequency.

In the next post, I will discuss -how to increase clock frequency by digital technique..